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Semiconductor business models and device scaling are facing challenges due to high
and write cycles in flash memories, and capacitor scaling limitations for dynamic
random access memory (DRAM) cells. The cost for double patterning with immersion
lithography and cost of ownership for next-generation lithography tools such as
extreme ultraviolet (EUV) are increasing sharply.

Hence, emerging memories, based on new material and device concepts such as
phase-change, magnetic, spintronics and resistive memories, are being developed.
However, it is difficult for emerging memories to catch up to the density of
conventional single-crystalline silicon memories because, fundamentally, the device
pattern density depends on the minimum lithography feature size, not on materials.
Further, material breakthroughs must be realized for these emerging memories to be
successful before market introduction. Therefore, it is generally believed that the
chance is slim for these emerging memories to penetrate majority memory markets in
the near future.

To overcome these challenges to the semiconductor business model and device
scaling, low-cost, high-density cell stacking in three-dimensional (3D) ICs is promising.
Unlike well-known 3D through-silicon vias (TSVs)—a package-level technology—the
true 3D IC must be able to stack high-density, multi-memory layers sequentially on
top of other device layers in a single chip at low cost using proven material and
device technologies.